There is known a semiconductor memory such as a flash memory having memory cells that is arranged in a matrix and is coupled to a control gate line, a selection gate line, a bit line, and a source line. Setting the control gate line, the selection gate line, the bit line, and the source line to predetermined voltages allows a program operation, an erasure operation, and a read operation of the memory cell to be executed. For example, generating hot electrons with a current fed from the source line to the bit line via a selection transistor and a memory transistor which receive a high level at a control gate and injecting the generated hot electrons into a floating gate of the memory cell arrow the program operation to be executed. Related arts are discussed in Japanese Laid-open Patent Publication No. 2008-226332, No. 2006-157050, No. 2004-30866, and No. 2001-351392.
In the program operation, if a voltage of the source line, to be set to a high level, coupled to the memory cell where data are to be programmed drops due to a leak current of the selection transistor coupled to the memory cell where data are not to be programmed, the hot electrons may not sufficiently be generated, and a program operation time may be long.